/KM06/
Alexander Krupp, Wolfgang Müller:
Classification Trees for Random Tests and Functional Coverage

DATE 2006, München, 2006

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Abstract:
This article presents the classification tree method for functional verification to close the gap from the specification of a test plan to SystemVerilog [1] testbench generation. Our method supports the systematic development of test configurations and is based on the classification tree method for embedded systems (CTM/ES) [2] extending CTM/ES for random test generation as well as for functional coverage and property specification. We support the structured coding of assertions and constraints by a twostep method: (i) creation of the classification tree (ii) creation of (sample) abstract test sequences. For SystemVerilog testbench generation, we introduce a mapping to SystemVerilog random tests, assertions, and functional coverage specifications. As our method is derived from the CTM/ES, it is also compliant to the V-method and thus applies to IEC61508-conformant development of electronic safety related systems. The remainder of this paper gives an overview of the classification tree method (CTM) before presenting our extension for functional verification.